1. Field of the Invention
The invention relates to clock and data recovery circuits. More particularly, the invention relates to frequency calibration of clock and data recovery circuits, such as burst mode clock and data recovery circuits.
2. Description of the Related Art
A clock and data recovery (CDR) circuit is a circuit that generates a periodic clock signal, or clock, that is synchronized with respect to an incoming data signal. CDR circuits often are used in communication systems to synchronize the phase relationship of the system's receiver to the incoming signal from the system's transmitter. One type of conventional clock recovery method recovers the phase of the incoming signals directly from information contained within the incoming signals themselves. Such clock recovery method can be achieved using either an open-loop configuration or a closed-loop configuration.
A burst mode CDR circuit is a circuit or circuit element that synchronizes or recovers timing information from a burst of formatted data applied or input to the CDR circuit. Conventional data formats include, e.g., the non-return-to-zero (NRZ) format, in which a “1” represents a logical high level or state and a “0” represents a logical low level or state. Such data format is compared with, e.g., the non-return-to-zero inverse (NRZI) format, in which a “1” represents a data state transition and a “0” represents the lack of a data state transition.
Many conventional CDR circuits use at least one gated oscillator, which is triggered by incoming data transitions, to create a local retiming clock that is synchronized to the incoming data signal. Such gated oscillator approach, in general, improves the circuit's performance with data signals that have relatively long strings of consecutive identical digits (CID), and generally requires less power and circuit area compared to other approaches, such as slaved oscillator approaches. For example, U.S. Pat. No. 5,237,290 tunes the gated oscillators using a slave circuit locked to a reference with a phase-locked loop (PLL), which generates a clock that has a constant phase relationship with a periodic input signal. However, physical differences in the circuits can cause the oscillator to run at different frequencies. Such frequency differences can reduce the system tolerance to CID data patterns.
Another gated oscillator CDR circuit, U.S. Pat. No. 5,834,980, makes use of a plurality of gated oscillators. In this configuration, one set of oscillators are being frequency calibrated while the other set of oscillators are active in the CDR circuit. Another CDR circuit configuration, U.S. Pat. No. 6,377,082, enhances the configuration disclosed in U.S. Pat. No. 5,834,980 by using a more digital approach to tune out frequency differences. However, both configurations add considerable circuit area to the overall CDR circuit.
Accordingly, it would be desirable to have a gated oscillator CDR circuit, suitable for use with relative significant CID data, that overcomes frequency mismatch problems, and yet requires less active circuitry than conventional arrangements.